1. Field of the Invention
The present invention generally relates to yield estimation techniques for large complex circuit designs and, more particularly, to an incremental method for critical area computation of shorts and opens in very large scale integrated (VLSI) circuits.
2. Description of the Prior Art
Yield prediction is of growing importance in modern VLSI design due to the need for reducing the cost of manufacturing. Yield estimation techniques for large complex designs are based on the concept of critical area which provides an analytical formulation for yield loss caused by defects occurring during fabrication.
For examples of state of the art yield prediction techniques, see, W. Maly and J. Deszczka, "Yield Estimation Model for VLSI Artwork Evaluation", Electron Lett., vol. 19, no. 6, pp. 226-227, March 1983, C. H. Stapper, "Modeling of defects in integrated circuits photolithographic patterns", IBM J. Research and Development, vol. 28, no. 4, pp. 461-475, 1984, W. Maly, "Modeling of lithography related yield losses for CAD of VLSI circuits" IEEE Transactions on Computer-Aided Design, vol. CAD-4, no. 3, pp. 166-177, July 1985, A. V. Ferris-Prabhu, "Modeling the Critical Area in Yield Forecast", IEEE Journal of Solid State Circuits, vol. SC-20, No. 4, Aug. 1985, pp. 874-878, J. Pineda de Gyvez and C. Di, IEEE Transactions on Computer-Aided Design, vol. 11, no. 5, pp. 638-658, May 1992, I. A. Wagner and I. Koren, "An Interactive VLSI CAD Tool for Yield Estimation", IEEE Transactions on Semiconductor Manufacturing, Vol. 8, No. 2, 1995, pp. 130-138, and C. H. Stapper and R. J. Rosner, "Integrated Circuit Yield Management and Yield Analysis: Development and Implementation" IEEE Transactions on Semiconductor Manufacturing, Vol.8, No.2, 1995, pp. 95-101).
Fabrication defects are caused by contaminants in materials and equipment. The formula used to compute critical area is the following according to
I. A. Wagner and I. Koren, ibid., ##EQU1## where A.sub.c denotes the critical area, A(r) denotes the area in which the center of a defect of radius r must fall in order to cause circuit failure, and D(r) is the density function of the defect size. Based on experimental data, D(r) is given by the following formula: ##EQU2## where p, q are real numbers (typically p=3, q=1), c=(q+1) (p-1)/(q+p), and r.sub.0 is some minimum optically resolvable size. See C. H. Stapper, ibid., A. V. Ferris-Prabhu, "Defect size variations and their effect on the critical area of VLSI devices", IEEE Journal of Solid State Circuits, vol. SC-20, No. 4, Aug. 1985, pp. 878-880, and I. Koren, "The effect of scaling on the yield of VLSI circuits", Yield Modeling and defect Tolerance in VLSI circuits, W. R. Moore, W. Maly, and A. Strojwas, Eds., Bristol UK: Adam-Hilger Ltd., 1988, pp. 91-99.
Essentially, there are two types of contamination caused manufacturing defects: extra material, causing shorts between different conducting regions and missing material, causing open circuits. Because of missing material we get two kinds of defects: breaks and via blocks. A break is an area of missing material that breaks a conducting region into two distinct pieces, therefore breaking an intended connection. Via blocks are missing material defects that overlap with vias and thus destroy the connection between elements of the same net in different layers. Among these different types of defects, shorts are the most important ones because they are the main reason for yield loss in current technologies.